MC68LC040RC25A Datasheet, PDF (163/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
BCLK
A31–A0
UPA1, UPA0
SIZ1, SIZ0
TT1, TT0
TM2–TM0
R/W
CIOUT
TS
TIP
TA
D31–D0
C1
C2
LONG
LONG-WORD
WRITE
Figure 7-15. Long-Word Write Transfer Timing
Clock 1 (C1)
The write cycle starts in C1. During the first half of C1, the processor places valid values
on the address bus and transfer attributes. For user and supervisor mode accesses,
which the corresponding memory unit translates, the UPAx signals are driven with the
values from the U1 and U0 bits for the area. The TTx and TMx signals identify the
specific access type. The R/W signal is driven low for a write cycle. CIOUT is asserted if
the access is identified as noncachable or if the access references an alternate address
space. Refer to Section 3 Memory Management Unit (Except MC68EC040 and
MC68EC040V) for information on the M68040 and MC68LC040 memory units and
Appendix B MC68EC040 for information on the MC68EC040 memory unit.
The processor asserts TS during C1 to indicate the beginning of a bus cycle. If not
already asserted from a previous bus cycle, the TIP signal is also asserted at this time
to indicate that a bus cycle is active.
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