MC68LC040RC25A Datasheet, PDF (405/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

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BCLK
RSTI
CDIS, MDIS*,
IPL2–IPL0
BUS
SIGNALS
TS
TIP
BR
BG
BB
MI
t > 10
CLOCKS
2
CLOCKS
128
CLOCKS
NOTE: * Not on MC68EC040V.
Figure C-3. MC68040V and MC68EC040V Normal Reset Timing
Resetting the processor causes any bus cycle in progress to terminate as if TA or TEA
had been asserted. In addition, the processor initializes registers appropriately for a reset
exception. When a RESET instruction is executed, the processor drives the reset out
(RSTO) signal for 512 BCLK cycles. In this case, the processor resets the external devices
of the system, and the internal registers of the processor are unaffected. The external
devices connected to the RSTO signal are reset at the completion of the RESET
instruction. An RSTI signal that is asserted to the processor during execution of a RESET
instruction immediately resets the processor and causes the RSTO signal to negate.
RSTO can be logically ANDed with the external signal driving RSTI to derive a system
reset signal that is asserted for both an external processor reset and execution of a
RESET instruction. It is necessary that the MC68040V and MC68EC040V be powered up
before other 5V devices; because the two power supplies must be within 2.5V of each
other.
C.5 POWER CYCLING
In cases were power is cycled off, then on with a duration of one second, RESET must be
asserted prior to removing power. This allows for an orderly shutdown within the
MC68040V and enables circuitry for the subsequent power-up.
MOTOROLA
M68040 USER’S MANUAL
C- 9
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