MC68LC040RC25A Datasheet, PDF (215/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

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such as those that generate locked bus transfers or access serialized pages, are allowed
to complete before exception processing begins.
Exception processing occurs in four functional steps. However, all individual bus cycles
associated with exception processing (vector acquisition, stacking, etc.) are not
guaranteed to occur in the order in which they are described in this section. Figure 8-1
illustrates a general flowchart for the steps taken by the processor during exception
processing.
During the first step, the processor makes an internal copy of the status register (SR).
Then the processor changes to the supervisor mode by setting the S-bit and inhibits
tracing of the exception handler by clearing the trace enable (T1 and T0) bits in the SR.
For the reset and interrupt exceptions, the processor also updates the interrupt priority
mask in the SR.
During the second step, the processor determines the vector number for the exception.
For interrupts, the processor performs an interrupt acknowledge bus cycle to obtain the
vector number. For all other exceptions, internal logic provides the vector number. This
vector number is used in the last step to calculate the address of the exception vector.
Throughout this section, vector numbers are given in decimal notation.
8-2
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