MC68LC040RC25A Datasheet, PDF (226/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

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level 6 interrupt, the SR mask is automatically updated with a value of 6 before entering
the handler routine so that subsequent level 6 interrupts and lower level interrupts are
masked. Provided no instruction that lowers the mask value is executed, the external
request can be lowered to level 3 and then raised back to level 6 and a second level 6
interrupt is not processed. However, if the M68040 is handling a level 7 interrupt (SR
mask set to level 7) and the external request is lowered to level 3 and than raised back to
level 7, a second level 7 interrupt is processed. The second level 7 interrupt is processed
because the level 7 interrupt is transition sensitive. A level comparison also generates a
level 7 interrupt if the request level and mask level are at 7 and the priority mask is then
set to a lower level (with the MOVE to SR or RTE instruction, for example). The level 6
interrupt request and mask level example in Figure 8-3 is the same as for all interrupt
levels except 7.
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