MC68LC040RC25A Datasheet, PDF (220/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
3. Instruction access faults occur when the PC section is deadlocked because of the
faulted data or another prefetch is required, the copyback stage is empty, and the
data cache and bus controller are idle. Since instruction access faults are reset, they
can be ignored.
4. An internal access fault also occurs when the data or instruction MMU detects that a
successful address translation is not possible because the page is write protected,
supervisor only, or nonresident. Furthermore, when an address translation cache
(ATC) miss occurs, the processor searches the translation tables in memory for the
mapping, and then retries the access. If a valid translation for the logical address is
not available due to a problem encountered during the table search, an internal
access fault occurs when the aborted access is retried. The problem encountered
could be either an invalid descriptor or the assertion of the TEA signal during a bus
cycle used to access the translation tables. A miss in the ATC causes the processor
to automatically initiate a table search but does not cause an internal access fault
unless one of the three previous conditions is encountered. However, this is not true
if the memory management unit (MMU) is disabled.
When an exception is detected, all parts of the execution unit either remain or are forced
to idle, at which time the highest priority exception is taken. Restarting the instruction or a
user-defined supervisor cleanup exception handler routine regenerates lower priority
exceptions on the return from exception handling. Internal access faults and bus errors
are reported after all other pending integer instructions complete execution. If an
exception is generated during completion of the earlier instructions, the pending
instruction fault is cleared, and the new exception is serviced first. The processor restarts
the pending prefetch after completing exception handling for the earlier instructions and
takes a bus error exception if the access faults again. For data access faults, the
processor aborts current instruction execution. If a data access fault is detected, the
processor waits for the current instruction prefetch bus cycle to complete, then begins
exception processing immediately.
As illustrated in Figure 8-1, the processor begins exception processing for an access fault
by making an internal copy of the current SR. The processor then enters the supervisor
mode and clears T1 and T0. The processor generates exception vector number 2 for the
access fault vector. It saves the vector offset, PC, and internal copy of the SR on the
stack. The saved PC value is the logical address of the instruction executing at the time
the fault was detected. This instruction is not necessarily the one that initiated the bus
cycle since the processor overlaps execution of instructions. It also saves information to
allow continuation after a fault during a MOVEM instruction and to support other pending
exceptions. The faulted address and pending write-back information is saved. The
information saved on the stack is sufficient to identify the cause of the bus error, complete
pending write-backs, and recover from the error. The exception handler must complete the
pending write-backs. Up to three write-backs can be pending for push errors and data
access errors.
If a bus error occurs during the exception processing for an access fault, address error, or
reset or while the processor is loading internal state information from the stack during the
execution of an RTE instruction, a double bus fault occurs, and the processor enters the
halted state as indicated by the PST3–PST0 encoding $5. In this case, the processor
MOTOROLA
M68040 USER’S MANUAL
8-7
For More Information On This Product,
Go to: www.freescale.com