MC68LC040RC25A Datasheet, PDF (49/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
2.2.2.5 CACHE CONTROL REGISTER. The CACR contains two enable bits that allow
the instruction and data caches to be independently enabled or disabled. Setting an
enable bit enables the associated cache without affecting the state of any lines within the
cache. A hardware reset clears the CACR, disabling both caches.
2-8
M68040 USER’S MANUAL
MOTOROLA
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