MC68LC040RC25A Datasheet, PDF (162/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
7.4.3 Byte, Word, and Long-Word Write Transfers
During a write transfer, the processor transfers data to a memory or peripheral device.
The level on the TCI signal is ignored by the processor during all write cycles. The bus
controller performs byte, word, and long-word write transfers for the following cases:
• Accesses to a disabled cache.
• Accesses to a memory page that is specified noncachable.
• Accesses that are implicitly noncachable (read-modify-write accesses and accesses
to an alternate logical address space via the MOVES instruction).
• Writes to write-through pages.
• Accesses that do not allocate in the data cache on a write miss (table updates and
exception stacking).
• The first transfer of a line write is terminated with TBI, forcing completion of the line
access using three additional long-word write transfers.
• Cache line pushes for lines containing a single dirty long word.
Figures 7-14 and 7-15 illustrate a flowchart and functional timing diagram for byte, word,
and long-word write bus transfers.
PROCESSOR
ADDRESS DEVICE
1) SET R/W TO WRITE
2) DRIVE ADDRESS ON A31–A0
3) DRIVE USER PAGE ATTRIBUTES ON UPA1, UPA0
4) DRIVE SIZE ON SIZ1, SIZ0 (BYTE, WORD, OR
LONG WORD)
5) DRIVE TRANSFER TYPE ON TT1, TT0
6) DRIVE TRANSFER MODIFIER ON TM2–TM0
7) CIOUT BECOMES VALID
8) ASSERT TS FOR ONE CLOCK
9) ASSERT TIP
10) DRIVE DATA ON APPROPRIATE BYTES OF
D31–D0 BASED ON SIZEx, A1, AND A0
TERMINATE TRANSFER
1) REMOVE DATA FROM D31–D0
2) NEGATE TIP (IF REQUIRED)
START NEXT CYCLE
EXTERNAL DEVICE
ACCEPT DATA
1) DECODE ADDRESS
2) LATCH DATA ON APPROPRIATE BYTES OF
D31–D0 BASED ON SIZEx, A1, AND A0
3) ASSERT TRANSFER ACKNOWLEDGE (TA)
TERMINATE CYCLE
1) NEGATE TA
Figure 7-14. Byte, Word, and Long-Word Write Transfer Flowchart
7-20
M68040 USER’S MANUAL
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