MC68LC040RC25A Datasheet, PDF (189/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
*BG Λ TSI Λ *BBI
BG Λ TSI
BBI Λ *BG Λ IBR Λ TSI
IDLE,
BBO DRIVEN BY
MC68040,
*THREE-STATED
*BG Λ *TSI Λ BBI
PROTOCOL
VIOLATION
BBI Λ *BG Λ *IBR Λ TSI
BG Λ TIP
BG
BG Λ *ENDCYCLE Λ TIP*
*BG Λ IBR
IMPLICIT
OWNERSHIP,
BBO DRIVEN BY
MC68040,
THREE-STATED
BG* Λ IBR
*BG
OWN/PARK,
*BBO DRIVEN BY
MC68040,
THREE-STATED
BG Λ ENDCYCLE
Λ *TIP
*ENDCYCLE Λ BBI Λ *BG Λ IBR
SNOOP,
BBO DRIVEN BY
MC68040,
*THREE-STATED
*ENDCYCLE Λ BBI Λ *BG Λ *IBR
BBI
BB
BBO
IBR _{D Q}
BR
BCLK
ENDCYCLE
IBR
BBI
TSI
ENDCYCLE
*
= Internal bus request signal (see schematic below).
= Bus busy driven by alternate bus master.
= Transfer start as an input, sampled by the MC68040.
= Whatever terminates a bus transaction
whether it is normal, bus error, or retried. Note
that false burst cycles are treated as a line
transaction. False locked transactions
are treated the same as any other bus cycle.
= The 040 may or may not transition if an active bus
cycle is terminated with a bus error, and BG is
asserted.
= Indicates the signal is asserted for that device.
Figure 7-30. M68040 Internal Interpretation State Diagram and
External Bus Arbiter Circuit
MOTOROLA
M68040 USER’S MANUAL
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