MC68LC040RC25A Datasheet, PDF (176/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
generates the vector number, which is the sum of the interrupt priority level plus 24 ($18).
There are seven distinct autovectors that can be used, corresponding to the seven levels
of interrupts available with IPL2–IPL0 signals. Figure 7-23 illustrates a functional timing
diagram for an autovector operation.
C1
C2
BCLK
C1
C2
A31–A0
UPA1, UPA0
SIZ1
SIZ0
TT1, TT0
TM2–TM0
BYTE
INTERRUPT LEVEL
R/W
CIOUT
TS
TIP
TA
AVEC
D31–D0
INTERRUPT
ACKNOWLEDGE
AUTOVECTORED
WRITE STACK
Figure 7-23. Autovector Interrupt Acknowledge Bus Cycle Timing
7.5.1.3 SPURIOUS INTERRUPT ACKNOWLEDGE BUS CYCLE. When a device does
not respond to an interrupt acknowledge bus cycle with TA, or AVEC and TA, the external
logic typically returns the transfer error acknowledge signal (TEA). In this case, the
M68040 automatically generates the spurious interrupt vector number 24 ($18) instead of
the interrupt vector number. If TA and TEA are both asserted, the processor retries the
cycle.
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M68040 USER’S MANUAL
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