MC68LC040RC25A Datasheet, PDF (30/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
1.7 DATA FORMAT SUMMARY
The M68040 supports the basic data formats of the M68000 family. Some data formats
apply only to the IU, some only to the FPU, and some to both. In addition, the instruction
set supports operations on other data formats such as memory addresses.
The operand data formats supported by the IU are the standard twos-complement data
formats defined in the M68000 family architecture plus a new data format (16-byte block)
for the MOVE16 instruction. Registers, memory, or instructions themselves can contain IU
operands. The operand size for each instruction is either explicitly encoded in the
instruction or implicitly defined by the instruction operation.
Whenever an integer is used in a floating-point operation, the FPU automatically converts
it to an extended-precision floating-point number before using the integer. The FPU
implements single- and double-precision floating-point data formats as defined by the
IEEE 754 standard. The FPU does not directly support packed decimal real format.
However, by trapping as an unimplemented data format instead of as an illegal instruction,
software emulation supports the packed decimal format. Additionally, each data format
has a special encoding that represents one of five data types: normalized numbers,
denormalized numbers, zeros, infinities, and not-a-numbers (NANs). Table 1-1 lists the
data formats for both the IU and the FPU. Refer to M68000PM/AD, M68000 Family
Programmer’s Reference Manual, for details on data format organization in registers and
memory.
Table 1-1. M68040 Data Formats
Operand Data Format
Bit
Bit Field
Binary-Coded Decimal (BCD)
Byte Integer
Word Integer
Long-Word Integer
Quad-Word Integer
16-Byte
Single-Precision Real
Double-Precision Real
Extended-Precision Real
Size
1 Bit
1–32 Bits
8 Bits
8 Bits
16 Bits
32 Bits
64 Bits
128 Bits
32 Bits
64 Bits
80 Bits
Supported In
IU
IU
IU
IU, FPU
IU, FPU
IU, FPU
IU
IU
FPU
FPU
FPU
Notes
—
Field of Consecutive Bits
Packed: 2 Digits/Byte; Unpacked: 1 Digit/Byte
—
—
—
Any Two Data Registers
Memory Only, Aligned to 16-Byte Boundary
1-Bit Sign, 8-Bit Exponent, 23-Bit Fraction
1-Bit Sign, 11-Bit Exponent, 52-Bit Fraction
1-Bit Sign, 15-Bit Exponent, 64-Bit Mantissa
1.8 ADDRESSING CAPABILITIES SUMMARY
The M68040 supports the basic addressing modes of the M68000 family. The register
indirect addressing modes support postincrement, predecrement, offset, and indexing,
which are particularly useful for handling data structures common to sophisticated
MOTOROLA
M68040 USER’S MANUAL
1-9
For More Information On This Product,
Go to: www.freescale.com