MC68LC040RC25A Datasheet, PDF (297/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
The separation of calculation and execution in the <ea> calculate and execute stages
allows instruction reordering during compile time to take advantage of potential instruction
overlap. Figure 10-2 illustrates this overlap for an instruction requiring multiple clocks in
the execute stage and with an instruction with a long lead time. The execution time for
LEA (3_L + 1) indicates that the instruction can be stalled three clocks without affecting
execution.
When the LEA (A) instruction precedes the ABCD (B) instruction, the execution stalls
during C4–C6 (equivalent to the LEA lead time) while the instruction completes in the
<ea> calculate and <ea> fetch stages. The resulting execution time for the LEA (A) and
ABCD (B) sequence is eight clocks.
However, if the LEA (C) instruction follows the ABCD (B) instruction, the LEA stalls in the
<ea> fetch instead, during C9–C11. The LEA then executes in a single clock in the
execution stage. The resulting execution time for the LEA (C) and ABCD (B) sequence is
five clocks.
LABEL
P1
A
B
C
N1
N2
INSTRUCTION
<ea>
CALCULATE
TRAPF
1
LEA $24(PC),A1
4
ABCD D0,D1
1
LEA $24(PC),A1
4
TRAPF
1
TRAPF
1
EXECUTE
1
3L + 1
3
3L + 1
1
1
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13
<ea> CALCULATE P1 A A A A B C C C C N1 N2
<ea> FETCH
P1 A A A A B C CL1 CL2 CL3 N1 N2
EXECUTE
P1 AL AL AL A B B B C* C N1
WRITE-BACK
NOTE: *Possible stalls in this stage.
Figure 10-2. Instruction Overlap with Multiple Clocks
10-6
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