MC68LC040RC25A Datasheet, PDF (334/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
DRIVE
TO 2.4 V
BCLK
1.5 V
DRIVE TO
0.5 V
A
B
OUTPUTS(1)
VALID ^{2.0 V}
OUTPUT ⁿ _{0.8 V}
1.5 V
2.0
V
0.8 V
VALID
OUTPUT
n+1
INPUTS(2)
RSTI (3)
DRIVE TO
2.4 V
DRIVE TO
0.5 V
C
2.0 V
VALID
0.8 V
INPUT
D
2.0 V
0.8 V
2.0 V
IPLx, CDIS,
MDIS
F
E
2.0 V
0.8 V
NOTES:
1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.
2. This input timing is applicable to all parameters specified relative to the rising edge of the clock.
3. This timing is applicable to all parameters specified relative to the negation of the RSTI signal.
LEGEND:
A. Maximum output delay specification.
B. Minimum output hold time.
C. Minimum input setup time specification.
D. Minimum input hold time specification.
E. Mode select setup time to RSTI negated.
F. Mode select hold time from RSTI negated.
Figure 11-2. Drive Levels and Test Points for AC Specifications
11-6
M68040 USER’S MANUAL
MOTOROLA
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