MC68LC040RC25A Datasheet, PDF (276/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
Table 9-12. Overflow Rounding Mode Values
Rounding
Mode
RN
RZ
RM
RP
Result
Infinity, with the sign of the intermediate result.
Largest magnitude number, with the sign of the intermediate result.
For positive overflow, largest positive number; for negative overflow, infinity.
For positive overflow, infinity; for negative overflow, largest negative number.
a. If the user OVFL exception handler is disabled, the M68040FPSP OVFL exception
handler checks for an INEX1 or INEX2 exception condition with the user INEX
exception handler enabled. If not, the processor returns to normal instruction flow.
Otherwise, the M68040FPSP OVFL exception handler restores the FPU to its
exceptional state, cleans up the stack to the conditions prior its execution, and
continues instruction execution at the user INEX exception handler. No parameters
are passed to the user INEX exception handler since the M68040FPSP OVFL
exception handler provides the illusion that it never existed. Otherwise, the
M68040FPSP OVFL exception handler returns the processor to normal processing.
b. If the user OVFL exception handler is enabled, the M68040FPSP OVFL restores the
FPU to its exceptional state, cleans up the stack to the conditions prior to execution,
and continues instruction execution at the user OVFL exception handler. No
parameters are passed to the user OVFL exception handler since the M68040FPSP
OVFL exception handler provides the illusion that it never existed.
The user OVFL exception handler must execute an FSAVE as its first floating-point
instruction. The destination contains the rounding mode values listed in Table 9-12, and
the user OVFL exception handler can choose to modify these values. The E3 and E1 bits
of the floating-point state frame are examined to determine which fields on the floating-
point state frame are valid. E3 always takes precedence and must be serviced first. Table
9-16 lists the floating-point state frame fields for OVFL exceptions with E3 set or with E3
clear and E1 set. Note that it is possible for an FADD, FSUB, FMUL, and FDIV to report a
post-instruction exception, although these instructions normally generate a pre-instruction
exception. The following example illustrates the reason why a post-instruction exception is
generated.
FADD
FMOVE
FP2,FP0
FP0, <ea>
; this instruction generates an overflow exception
; this instruction is executing when overflow occurs
In this example, assume that the FMOVE instruction starts once the FADD instruction
generates an overflow. Given the register dependency on FP0, the destination of the
FADD instruction, FP0 needs to be resolved prior to FMOVE instruction execution. For
this example, there is no choice but to have the FADD instruction report a post-instruction
exception immediately. Note that for this case, even though the T-bit of the floating-point
state frame is set, (post-instruction exception), it does not imply an FMOVE OUT
instruction. Therefore, the effective address field in the format $3 stack frame is invalid.
The FMOVE OUT instruction generates a post-instruction exception. For this case, the
effective address field in the format $3 stack frame points to the destination memory
location. If the destination is an integer data register, the FPIAR points to the F-line word
9-32
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