MC68LC040RC25A Datasheet, PDF (144/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
negate logic levels. The exceptions to this rule are the TIP, TA, and B B signals that
transition between logic levels during T4 but transition from a driven state to a high-
impedance state during T1. The input setup time (t_su), input hold time (t_hi), output hold
time (t_ho), and delay time (t_d) illustrated in Figure 7-1 are described in the AC electrical
timing specifications in Section 11 MC68040 Electrical and Thermal Characteristics.
BCLK
INTERNALLY
PHASE-LOCKED
PCLK
OUTPUTS
INPUTS
T1
T2
T3
T4
T1
td
t _d'
tho
t _ho'
t _su
t _hi
NOTES:
1. td = Propagation delay of signal relative to BLK rising edge.
2. ^td' = Propagation delay of signal relative to PCLK falling edge.; ^{td'= td} –1/2 PCLK
except for TIP, TA, BB when used as outputs.
3. ^tho = Output hold time relative to BCLK rising edge.
4. ^tho' = Output hold time relative to BCLK rising edge; ^{tho'= t} h –1/2 PCLK.
5. ^tsu = Required input setup time relative to BCLK rising edge.
6. ^thi = Required input hold time relative to BCLK rising edge.
Figure 7-1. Signal Relationships to Clocks
Inputs to the M68040 (other than the IPL2–IPL0 and RSTI signals) are synchronously
sampled and must be stable during the sample window defined by t_su, t_hi, and t_ho (see
Figure 7-1) to guarantee proper operation. The asynchronous IPL≈ and RSTI signals are
also sampled on the rising edge of BCLK, but are internally synchronized to resolve the
input to a valid level before using it. Since the timing specifications for the M68040 are
referenced to the rising edge of BCLK, they are valid only for the specified operating
frequency and must be scaled for lower operating frequencies.
7-2
M68040 USER’S MANUAL
MOTOROLA
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