MC68LC040RC25A Datasheet, PDF (81/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
ENTRY
OTHERWISE
LOGICAL ADDRESS
MATCHES WITH
TTRx*
ATC MISS
ATC HIT
OTHERWISE
LOGICAL ADDRESS
MATCHES WITH TTR0*
(R = 0) OR
[(W = 1) AND
(WRITE OR RMW CYCLE)]
(TTR1*[W] = 1) AND
(WRITE OR RMW
ACCESS)
OTHERWISE
(TTR0*[W] = 1) AND
(WRITE OR RMW
ACCESS)
OTHERWISE
ABORT CYCLE
TAKE ACCESS ERROR
EXCEPTION
OTHERWISE
ABORT CYCLE
(M = 0) AND
(WRITE OR RMW CYCLE)
OTHERWISE
TAKE ACCESS ERROR
EXCEPTION
PA LOGICAL ADDRESS
UPA TTR1* [U1,U0]
CM TTR1* [CM]
PA LOGICAL ADDRESS
UPA TTR0* [U1,U0]
CM TTR0* [CM]
ABORT CYCLE
TABLE SEARCH
OPERATION
EXIT
EXIT
PA ATC ENTRY [PA]
UPA ATC ENTRY [U1,U0]
CM ATC ENTRY [CM]
EXIT
* Refers to either instruction or data transparent translation register.
Figure 3-22. Address Translation Flowchart
3-32
M68040 USER'S MANUAL
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