MC68LC040RC25A Datasheet, PDF (193/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
Figure 7-33 illustrates a functional timing diagram for an arbitration of a relinquish and
retry operation. Figure 7-34 is a functional timing diagram for implicit ownership of the bus.
In Figure 7-33, the processor read access that begins in C1 is terminated at the end of C2
with a retry request and BG negated, forcing the processor to relinquish the bus and allow
the alternate master to access the bus. Note that the processor reasserts BR during C3
since the original access is pending again. After alternate bus master ownership, the bus
is granted to the processor to allow it to retry the access beginning in C7.
C1
C2
C3
C4
C5
C6
C7
C8
BCLK
A31–A0
TRANSFER
ATTRIBUTES
R/W
TS
TIP
TA
TEA
D31–D0
BR
BG
BB
AM_BR*
AM_BG*
PROCESSOR
* AM indicates the alternate bus master.
ALTERNATE
MASTER
PROCESSOR
Figure 7-33. Arbitration During Relinquish and Retry Timing
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M68040 USER’S MANUAL
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