MC68LC040RC25A Datasheet, PDF (344/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
Maximum power dissipation in the large buffer mode occurs for output:
Low: P_llb = I²R = (49.6 mA)² x 6 Ω = 14.8 mW
High: P_hlb = I²R = (50.8 mA)² x 12 Ω = 30.1 mW
Similar calculations for unterminated small buffers yield:
I = 5 mA (by spec)
and
P = I²R = (5 mA)² x 25 Ω
so
P_hsb = 0.625 mW
P_lsb = 0.625 mW
Assuming that the duty cycle of output j is driving a valid logic value instead of being
three-stated as given by DCj, then the following equation approximates total average
power dissipation in the output buffers:
Number of
Outputs Used
∑ ^ITotal ^{= (I}j ^{× DC}j^{)2 × R}effj
j=1
I_j and Z_oj are calculated for every pin as illustrated above. In practice the above
summation is carried out by groups of pins instead of individual pins.
Motorola has calculated the values for DC_j for typical situations. On an average clock
there will be 37.8 pins high, 41.5 pins low, and 11.7 pins three-stated. The following
examples demonstrate how to calculate the power dissipation that is added to small buffer
power dissipation numbers, assuming a termination as illustrated in Figure 11-18.
a. For the numbers listed in this section in a large buffer design with no caching.
P = (Number of Pins High) × (P_hlb) + (Number of Pins Low) × (P_llb)
= 37.8 Pins × 30.1 mW per Pin + 41.5 Pins × 14.8 mW per Pin
= 1.75 W
b. For a single bus master system in a large buffer design with no caching or snooping
and only standard features (i.e., TLN, UPA, BR, BB, LOCK, LOCKE, CIOUT, TIP, MI,
TDO, IPEND, PST not used):
P = (Number of Pins High) × (P_hlb) + (Number of Pins Low) × (P_llb)
= 29.8 Pins × 30.1 mW per Pin + 34.5 Pins × 14.8 mW per Pin
= 1.41 W
c. For the example b system with copyback caching, assuming 85% cache hit rate:
P = (29.8 Pins × 30.1 mW per Pin + 34.5 Pins × 14.8 mW per Pin) × (1 – 0.85)
= 0.21 W
11-16
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