MC68LC040RC25A Datasheet, PDF (303/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
10.5 MISCELLANEOUS INTEGER UNIT INSTRUCTION TIMINGS
(Continued)
Instruction
Condition
<ea> Calculate Execute
ORI #<xxx>,CCR
ORI #<xxx>,SRa
PACK
PFLUSH ^b
PFLUSHA ^b
PFLUSHANb
PFLUSHN (An)b
PTESTR, PTESTWe
RESETa
RTDc
RTE ^a
RTRc
RTS ^c
—
—
Dx,Dy,#<xxx>
–(Ay),–(Ax),#<xxx>
—
—
—
—
—
—
—
Stack Format $0
Stack Format $1
Stack Format $2
Stack Format $3
Stack Format $4
Stack Format $7
—
—
1
4
9
1L + 8
1
3
3
2L + 3
11
1L + 10
11
1L + 10
27
1L + 26
11
1L + 10
25
11L + 14
521
521
6
1L + 5
2
13
4
23
2
14
3
20
2
15
4
23
7
1L + 6
5
5
SBCD
SUBX
SWAP
TRAP#a
TRAPccf
TRAPVf
Dy,Dx
–(Ay),–(Ax)
Dy,Dx
–(Ay),–(Ax)
—
—
Taken
Not Taken
Taken
Not Taken
1
3
3
1L + 3
1
1
3
1L + 2
1
2
16
16
19
19
5
5
19
19
5
5
UNLK
—
2
1L + 1
UNPK
Dx,Dy,#
–(Ay),–(Ax),#
1
4
3
2L + 4
NOTES:
a. Times listed are minimum. This instruction interlocks the <ea> calculate and execute
stages and synchronizes some portions of the processor before execution.
b. Times listed are typical. This instruction interlocks the <ea> calculate and execute stages
and synchronizes some portions of the processor before execution.
c. This instruction interlocks the <ea> calculate and execute stages.
d. Successive in-line MOVE16 instructions each add eight clocks to the <ea> calculate and
execute times.
e. Typical measurement for three-level table search with no descriptor writes, no entries
cached, and four-clock memory access times.
f. This instruction interlocks the <ea> calculate and execute stages. For the exception taken,
this instruction also synchronizes some portions of the processor before execution; times
listed are minimum in this case.
10-12
M68040 USER’S MANUAL
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