MC68LC040RC25A Datasheet, PDF (418/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
C.7.6 Output AC Timing Specifications (see Figures C-13* to C-21)
PRELIMIINARY
0–16.67 MHz
25 MHz
33 MHz
Num
Characteristic
Min Max Min Max Min Max Unit
BCLK to Address, CIOUT , LOCK, LOCKE ,
11
PSTx, R/W, SIZx, TLNx, TMx, TTx, UPAx
Valid
9
30
9
30 6.5
25
ns
12
BCLK to Output Invalid (Output Hold)
9
—
9
— 6.5
—
ns
13
BCLK to TS Valid
9
30
9
30 6.5
25
ns
14
BCLK to TIP Valid
9
30
9
30 6.5
25
ns
18
BCLK to Data-Out Valid
9
32
9
32 6.5
27
ns
19
BCLK to Data-Out Invalid (Output Hold)
9
—
9
— 6.5
—
ns
20
BCLK to Output Low Impedance
9
—
9
— 6.5
—
ns
21
BCLK to Data-Out High Impedance
9
20
9
20 6.5
17
ns
BCLK to Address, CIOUT , LOCK, LOCKE ,
38
R/W , SIZx, TS, TLNx, TMx, TTx, UPAx High
Impedance
9
18
9
18 6.5
15
ns
39
BCLK to BB, TA, TIP High Impedance
19
28
19 28
14
25
ns
40
BCLK to BR , BB Valid
9
30
9
30 6.5
23
ns
43
BCLK to MI Valid
9
30
9
30 6.5
25
ns
48
BCLK to TA Valid
9
30
9
30 6.5
25
ns
50
BCLK to IPEND, PSTx, RSTO Valid
9
30
9
30 6.5
25
ns
W
RSTI active to SCD inactive.
8
100
8
100
8
100
ns
A
IPL≈ to SCD invalid
8
100
8
100
8
100
ns
NOTE:
* Output timing is specified for a valid signal measured at the pin. Timing is specified driving an unterminated
30-Ω transmission line with a length characterized by a 2.5-ns one-way propagation delay. Buffer output
impedance is typically 30 Ω; the buffer specifications include approximately 5 ns for the signal to propagate
the length of the transmission line and back.
C-22
M68040 USER’S MANUAL
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