MC68LC040RC25A Datasheet, PDF (184/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
On the initial cycle of a line transfer, a retry causes the processor to retry the bus cycle as
illustrated in Figure 7-29. However, the processor recognizes a retry signaled during the
second, third, or fourth cycle of a line as a bus error and causes the processor to abort the
line transfer. A burst-inhibited line transfer can only be retried on the initial transfer. A
burst-inhibited line transfer aborts if a retry is signaled for any of the three long-word
transfers used to complete the line transfer. Negating the bus grant (BG) signal on the
M68040 while asserting both TA and TEA provides a relinquish and retry operation for any
bus cycle that can be retried (see Figure 7-31).
C1
C2
C1
C2
C3
C4
C5
BCLK
A31–A0
UPA1, UPA0
SIZ1, SIZ0
LINE
TT1, TT0
TM2–TM0
R/W
CIOUT
TS
TIP
TA
TEA
TBI
D31–D0
RETRY
SIGNALED
RETRY CYCLE
Figure 7-29. Retry Operation on Line Write
7-42
M68040 USER’S MANUAL
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