MC68LC040RC25A Datasheet, PDF (25/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
more common case of the branch taken, and both execution paths of the branch are
fetched and decoded to minimize refilling of the instruction pipeline.
INSTRUCTION DATA BUS
CONVERT
EXECUTE
WRITE-
BACK
FLOATING-
POINT
UNIT
INSTRUCTION
FETCH
DECODE
EA
CALCULATE
EA
FETCH
EXECUTE
WRITE-
BACK
INTEGER
UNIT
INSTRUCTION
ATC
INSTRUCTION
CACHE
INSTRUCTION
MMU/CACHE/SNOOP
CONTROLLER
INSTRUCTION MEMORY UNIT
INSTRUCTION
ADDRESS
B
U
S
DATA MEMORY UNIT
DATA
MMU/CACHE/SNOOP
CONTROLLER
C
O
N
T
R
O
L
DATA
L
ADDRESS
E
R
DATA
ATC
DATA
CACHE
ADDRESS
BUS
DATA
BUS
BUS
CONTROL
SIGNALS
OPERAND DATA BUS
Figure 1-1. Block Diagram
To improve memory management, the M68040 includes separate, independent paged
MMUs for instruction and data accesses. Each MMU stores recently used address
mappings in separate 64-entry address translation caches (ATCs). Each MMU also has
two transparent translation registers that define a one-to-one mapping for address space
segments ranging in size from 16 Mbytes to 4 Gbytes each.
Two memory units independently interface with the IU and FPU. Each unit consists of an
MMU, an ATC, a main cache, and a snoop controller. The MMUs perform memory
management on a demand-page basis. By translating logical-to-physical addresses using
translation tables stored in memory, the MMUs support virtual memory systems. Each
MMU stores recently used address mappings in an ATC, reducing the average translation
time.
Separate on-chip instruction and data caches operate independently and are accessed in
parallel with address translation. The caches improve the overall performance of the
system by reducing the number of bus transfers required by the processor to fetch
information from memory and by increasing the bus bandwidth available for alternate bus
1-4
M68040 USER’S MANUAL
MOTOROLA
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