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MC68LC040RC25A Datasheet, PDF (234/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual
Freescale Semiconductor, Inc.
8.4.1 Four-Word Stack Frame (Format $0)
If a four-word stack frame is on the active stack and an RTE instruction is encountered,
the processor updates the SR and PC with the data read from the stack, increments the
stack pointer by eight, and resumes normal instruction execution.
Stack Frames
15
0
SP
STATUS REGISTER
+$02
PROGRAM COUNTER
+$06
0000
VECTOR OFFSET
FOUR-WORD STACK FRAME–FORMAT $0
Exception Types
• Interrupt
• Format Error
• TRAP #N
• Illegal Instruction
• A-Line Instruction
• F-Line Instruction
• Privilege Violation
• Floating-Point Pre-
Instruction
Stacked PC Points To
• Next Instruction
• RTE or RESTORE
Instruction
• Next Instruction
• Illegal Instruction
• A-Line Instruction
• F-Line Instruction
• First Word of Instruction
Causing Privilege Violation
• Floating-Point Pre-
Instruction Exception
8.4.2 Four-Word Throwaway Stack Frame (Format $1)
If a four-word throwaway stack frame is on the active stack and an RTE instruction is
encountered, the processor increments the active stack pointer by eight, updates the SR
with the value read from the stack, and then begins RTE processing again, as illustrated in
Figure 8-6. The processor reads a new format word from the stack frame on top of the
active stack (which may or may not be the same stack used for the previous operation)
and performs the proper operations corresponding to that format. In most cases, the
throwaway frame is on the interrupt stack, and when the SR value is read from the stack,
the S-bit and M-bit are set. In that case, there is a normal four-word frame on the master
stack. However, the second frame can be any format (even another throwaway frame)
and can reside on any of the three system stacks.
Stack Frames
15
0
SP
STATUS REGISTER
+$02
PROGRAM COUNTER
+$06
0001
VECTOR OFFSET
THROWAWAY FOUR-WORD STACK FRAME–FORMAT $1
Exception Types
• Created on interrupt stack
during interrupt exception
processing when transition
from master state to
interrupt state occurs.
Stacked PC Points To
• Next Instruction: same as
on master stack.
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