MC68LC040RC25A Datasheet, PDF (195/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

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how the LOCKE signal can be used to end a locked sequence and to yield the bus one
bus cycle earlier than is normally possible. Figure 7-35 illustrates the state diagram of a
hypothetical external arbiter design.
BB Λ LOCK* V BB Λ
LOCK Λ LOCKE
STATE D
BG1*, BG2
BB*
BB Λ LOCK Λ LOCKE*
BR1 Λ LOCK Λ LOCKE
V BR1 Λ LOCK*
STATE C
BG1, BG2*
BR1* V BR1 Λ
LOCK Λ LOCKE*
BB*
BR2* V
BR2 Λ LOCK Λ LOCKE
BG1*, BG2
STATE A
BR2 Λ LOCK Λ LOCKE
V BR2 Λ LOCK*
BG1, BG2*
STATE B
BB Λ LOCK* V BB Λ
LOCK Λ LOCKE
NOTES:
BB Λ LOCK Λ LOCKE*
1. Because this example uses two MC68040s, 1 and 2 refer to the processor and its signals.
2. *Indicates the signal is asserted for that device.
Figure 7-35. Dual M68040 Fairness Arbitration State Diagram
Assuming that processor 1 currently owns the bus, the external arbiter is in state A. If
processor 2 asserts BR2, then processor 1 behaves in one of three ways:
1. If processor 1 is currently in the middle of a nonlocked bus access, then the external
arbiter proceeds to state B, in which BG1 is negated and BG2 is asserted. The
external arbiter then proceeds to state C only when BB is negated, signifying the end
of the bus cycle.
2. If processor 1 is currently in the middle of a locked bus access, then the external
arbiter stays in state A until LOCKE is asserted. Once LOCKE is asserted, the
external arbiter enters state B, in which BG1 is negated and BG2 is asserted. The
external arbiter proceeds to state C once BB is negated, signifying the end of the
bus cycle.
3. If processor 1 is in one of the three boundary conditions, then the external arbiter
proceeds to state B. During state B, the external arbiter checks for the possibility of a
newly initiated locked bus access. If it detects a locked bus cycle, it returns the bus
to processor 1 by entering state A. Note that even though processor 1 recognizes
BG1 is asserted, it does not take the bus because processor 1 asserts BB whenever
the boundary condition results in processor 1 performing another bus cycle. The
external arbiter stays in state A until LOCKE is asserted, then proceeds to state B to
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