MC68LC040RC25A Datasheet, PDF (419/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
C.7.7 Input AC Timing Specifications (See Figures C-13 to C-21)
PRELIMINARY
0–16.67 MHz
Num
Characteristic
Min Max
15
Data-In Valid to BCLK (Setup)
5
—
16
BCLK to Data-In Invalid (Hold)
4
—
17
BCLK to Data-In High Impedance (Read
Followed by Write)
—
49
22a TA Valid to BCLK (Setup)
10
—
22b TEA Valid to BCLK (Setup)
10
—
22c TCI Valid to BCLK (Setup)
10
—
22d TBI Valid to BCLK (Setup)
11
—
23
BCLK to TA, TEA, TCI , TBI Invalid (Hold)
2
—
24
AVEC Valid to BCLK (Setup)
5
—
25
BCLK to AVEC Invalid (Hold)
2
—
41a BB Valid to BCLK (Setup)
7
—
41b BG Valid to BCLK (Setup)
8
—
41c CDIS , MDIS* Valid to BCLK (Setup)
10
—
41d IPL≈ Valid to BCLK (Setup)
4
—
42
BCLK to BB, BG, CDIS, MDIS* , IPL≈ Invalid
(Hold)
2
—
44a Address Valid to BCLK (Setup)
8
—
44b SIZx Valid to BCLK (Setup)
12
—
44c TTx Valid to BCLK (Setup)
6
—
44d R/W Valid to BCLK (Setup)
6
—
44e SCx Valid to BCLK (Setup)
10
—
45
BCLK to Address SIZx, TTx, R/W , SCx
Invalid (Hold)
2
—
46
TS Valid to BCLK (Setup)
5
—
47
BCLK to TS Invalid (Hold)
2
—
49
BCLK to BB High Impedance
(Processor Assumes Bus Mastership)
—
9
51
RSTI Valid to BCLK
5
—
52 BCLK to RSTI Invalid
2
—
B
LFO change to valid IPL≈ , RSTI (setup)
5
—
D
IPEND valid to IPL≈ invalid (Hold)
0
—
V
RSTI pulse width, leaving LPSTOP mode
10
—
Z
IPL≈, RSTI valid to LFO change (Hold)
500
—
NOTE: *Not on the MC68EC040V.
25 MHz
Min Max
5
—
4
—
—
49
10
—
10
—
10
—
11
—
2
—
5
—
2
—
7
—
8
—
10
—
4
—
2
—
8
—
12
—
6
—
6
—
10
—
2
—
5
—
2
—
—
9
5
—
2
—
5
—
0
—
10
—
500
—
33 MHz
Min Max Unit
4
—
ns
4
—
ns
— 36.5 ns
10
—
ns
10
—
ns
10
—
ns
10
—
ns
2
—
ns
5
—
ns
2
—
ns
7
—
ns
7
—
ns
8
—
ns
3
—
ns
2
—
ns
7
—
ns
8
—
ns
8.5
—
ns
5
—
ns
11
—
ns
2
—
ns
9
—
ns
2
—
ns
—
9
ns
4
—
ns
2
—
ns
5
ns
0
—
ns
10
—
ns
500
—
ns
MOTOROLA
M68040 USER’S MANUAL
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C- 23