MC68LC040RC25A Datasheet, PDF (197/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

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BB Λ BR2*
STATE D
BG1*, BG2
BB*
BB Λ BR2
BR1 Λ BR2*
STATE C
BG1, BG2*
BR2 V BR1*Λ
BR2*
BB*
BR2* V
BR2 Λ LOCK Λ LOCKE*
BG1*, BG2
STATE A
BR2 Λ LOCK Λ LOCKE
V BR2 Λ LOCK*
BG1, BG2*
STATE B
BB Λ LOCK* V BB &
LOCK Λ LOCKE
BB Λ LOCK Λ LOCKE*
NOTES:
1. Because this example uses two MC68040s, 1 or 2 refers to the processor and its signals.
2. *Indicates the signal is asserted for that device.
Figure 7-36. Dual M68040 Prioritized Arbitration State Diagram
7.8.2.3 M68040 SYNCHRONOUS DMA ARBITRATION. Figure 7-37 illustrates a system
with an M68040 and a synchronous direct memory access (DMA) that contains an
M68040 interface. Figure 7-37(a) illustrates that the DMA owning the bus only when the
M68040 has no pending requests, and Figure 7-37(b) illustrates the DMA having higher
priority than the M68040 causing the M68040 to yield the bus to the DMA at any time
except when the M68040 is performing a locked bus operation. In either case, the M68040
is the default bus master; if there are no pending requests from either device, the external
arbiter gives the bus to the M68040. Similar to the M68040 fairness arbitration example,
the restriction on using LOCKE applies to this example.
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M68040 USER’S MANUAL
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