MC68LC040RC25A Datasheet, PDF (212/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
transfer. Edge-triggered latch B is clocked by the rising edge of BCLK and latches the
data from latch A for use by internal logic.
EXTERNAL
DATA BUS
TRANSPARENT
LATCH - A
DQ
G
EDGE-TRIGGERED
LATCH - B
DQ
WRITE DATA
LATCHED
READ DATA
DLE
BCLK
TA, TEA, TBI
TERMINATION
CONTROL
Figure 7-47. DLE Mode Block Diagram
Figure 7-48 illustrates the data read timing for both normal operation and DLE mode.
During normal operation (i.e., DLE mode disabled), latch A is always transparent, and by
the rising edge of BCLK, read data is latched. Data must meet setup and hold time
specifications #15 and #16 in this case. When the DLE mode is enabled, the data can be
latched by the rising edge of BCLK or the falling edge of DLE, depending on the timing for
DLE.
7-70
M68040 USER’S MANUAL
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