MC68LC040RC25A Datasheet, PDF (245/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
SECTION 9
FLOATING-POINT UNIT (MC68040 ONLY)
NOTE
This section does not apply to the MC68040V, MC68LC040,
MC68EC040, or MC68EC040V. Refer to Appendix A
MC68LC040 and Appendix B MC68EC040 for details.
Floating-point math refers to numeric calculations with a variable decimal point location. It
is distinguished from integer math, which deals only with whole numbers and fixed
decimal point locations. Historically, general-purpose microprocessors have had to
depend on add-on coprocessors and accelerators such as the MC68881/MC68882 for fast
floating-point capabilities. The MC68040 features a built-in floating-point unit (FPU).
Consolidating this important function on chip speeds up the overall processing and
eliminates some interfacing overhead required for external accelerators. The MC68040
FPU operates in parallel with the integer unit (IU). The FPU does the numeric calculation
while the IU moves on to other tasks. Like the IU, the FPU has its own three-stage
pipeline overlapping operations such as integer to floating-point conversion, instruction
execution, and write-back. When used with the M68040FPSP, the MC68040 FPU is fully
compliant with IEEE floating-point standards.
9.1 FLOATING-POINT UNIT PIPELINE
Integer data from memory (memory to register) requires a pass through the FPU pipeline,
converting the data to the extended-precision format for the FPU to use. The result of this
conversion is presented to the conversion stage of the FPU pipeline where the desired
operation begins, starting a second pass through the pipeline. The IU is then released to
execute other instructions once the data has been transferred to the FPU.
Floating-point data to memory (register to memory) requires a complete pass through the
FPU pipeline, converting the data from the extended-precision format to an integer data
format. Register-to-memory instructions are normally handled entirely by the conversion
stage of the pipeline where the data move to memory operation completes. The IU is not
released until it has received the converted data (during the last conversion unit cycle).
Like the IU, the FPU has been optimized for the most frequently used instructions and
data types to provide the highest possible performance. To boost performance further, the
FMOVE instruction concurrently executes with arithmetic calculations and executes
completely transparent to the user. Instructions can execute nonsequentially as long as
there are no register dependencies. Refer to Section 10 Instruction Timings for details
on floating-point timings.
MOTOROLA
M68040 USER’S MANUAL
9-1
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