MC68LC040RC25A Datasheet, PDF (271/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
4. Examining the conditional predicate and setting the FPCC NAN bit accordingly
prevents the exception from being taken again. This technique gives the most
control since it is possible to pre-determine the direction of program flow. Bit 7 of the
F-line operation word indicates where the conditional predicate is located. If bit 7 is
set, the conditional predicate is the lower six bits of the F-line operation word.
Otherwise, the conditional predicate is the lower six bits of the instruction word,
which immediately follows the F-line operation word. Using the conditional predicate
and the table for IEEE nonaware test in 9.5.2 Conditional Testing, the condition
codes can be set to return a known result indication when the conditional instruction
is reexecuted.
Prior to exiting the user BSUN exception handler, the exception handler discards the
floating-point state frame.
9.7.1.2 NONMASKABLE EXCEPTION CONDITIONS. There are no conditions.
9.7.2 Signaling Not-a-Number (SNAN)
An SNAN is used as an escape mechanism for a user-defined, non-IEEE data type. The
processor never creates an SNAN as a result of an operation; a NAN created by an
operand error exception is always a nonsignaling NAN. When an operand is an SNAN
involved in an arithmetic instruction, the SNAN bit is set in the FPSR EXC byte. Since the
FMOVEM, FMOVE FPCR, and FSAVE instructions do not modify the status bits, they
cannot generate exceptions. Therefore, these instructions are useful for manipulating
SNANs.
9.7.2.1 MASKABLE EXCEPTION CONDITIONS. When an SNAN is encountered, if the
destination is a floating-point data register or is in memory (or an integer data register) and
the format is single, double, or extended precision, the SNAN is maskable and may or
may not take an exception.
a. If the user SNAN exception is disabled, the processor clears the SNAN bit in the
NAN data format and the resulting nonsignaling NAN is transferred to the
destination. No bits other than the SNAN bit of the NAN data format are modified,
although the input NAN is truncated if necessary. Instruction execution continues
without taking any exceptions.
b. If the user SNAN exception handler is enabled, the processor posts an exception
and another floating-point instruction is eventually encountered; a pre-instruction
exception is reported at that time. The SNAN entry in the processor’s vector table
points to the M68040FPSP SNAN exception handler. Once the M68040FPSP SNAN
exception handler recognizes the operand error as a maskable condition, it does not
modify the destination or pass control to the user SNAN exception handler.
9.7.2.2 NONMASKABLE EXCEPTION CONDITIONS. When an SNAN is encountered, if
the destination is either in memory or an integer data register and the format is byte, word,
or long word, a nonmaskable post-instruction exception occurs and is taken immediately.
The SNAN entry in the processor’s vector table points to the M68040FPSP SNAN
exception handler.
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