MC68LC040RC25A Datasheet, PDF (289/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
Table 9-16. State Frame Field Information (Continued)
FSAVE State
Frame Field
CMDREG1B
ETEMP
STAG
E1
T
CMDREG1B
ETEMP
STAG
FPTEMP
DTAG
E1
T
CMDREG1B
ETEMP
STAG
WBTEMP
E1
T
CMDREG1B
FPTEMP
STAG
E1
T
CMDREG3B
WBTEMP
WBTE15
E3
T
Contents
SNAN (For Opclass 011)
FMOVE Instruction Command Word
Unrounded Source Operand from Floating-Point Register, with SNAN bit set.
Source Operand Tag, indicated NAN.
Always 1
Always 1
OPERR (For Opclass 000 and 010)
Exception Instruction Command Word
Source operand is converted to extended precision.
Source Operand Tag
Destination operand, if any, is converted to extended precision.
Destination operand tag, if any.
Always 1
Always 0
OPERR (For Opclass 011)
FMOVE Instruction Command Word
Unrounded Source Operand from Floating-Point Register
Source Operand Tag
Contains the rounded integer used to check for erroneous integer overflow.
Always 1
Always 1
OVFL (FMOVE to Register, FABS, and FNEG)
Exception Instruction Command Word
Intermediate result with mantissa rounded to correct precision.
Source Operand Tag = Normalized
Always 1
Always 0
OVFL (FADD, FSUB, FMUL, FDIV, and FSQRT)
Encoded Exception Instruction Command Word
WBTS, WBTE, and WBTM equal the intermediate result with mantissa rounded
to the correct precision.
Bit 15 of the intermediate result's 16-bit exponent = 0 for overflow.
Always 1
Either 1 or 0
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