MC68LC040RC25A Datasheet, PDF (265/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

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exception and the F-line illegal instruction share the same vector, the exception handler
uses the stack frame format ($0 or $2) to distinguish between the two.
Table 9-10. Unimplemented Instructions
FACOS
FASIN
FATAN
FATANH
FCOS
FCOSH
FETOX
FETOXM1
FGETEXP
FGETMAN
FINT
FTWOTOX
FMOD
FSCALE
Monadic Operations
Dyadic Operations
FINTRZ
FLOG10
FLOGN
FLOGNP1
FMOVECR
FSIN
FSINCOS
FSINH
FTAN
FTANH
FTENTOX
—
FREM
—
When an unimplemented floating-point instruction is encountered, the processor waits for
all previous floating-point instructions to complete execution. Pending exceptions are
taken and handled prior to the execution of the unimplemented instruction.
Next, the instruction is partially decoded to allow fetching of the memory source operand,
if required. When the operand fetch begins, all other read accesses for previous
instructions are complete, and only the execution and write-back of results for previous
integer instructions remains to be completed. If an access error (bus error) occurs in
fetching the operand or in completing any other access before beginning the operand
fetch, the unimplemented instruction is restarted after the processor returns from
exception handling for the error. Refer to Section 8 Exception Processing for more
information on access errors.
The fetched source operand is passed to the FPU, which converts the operand to
extended precision and saves the intermediate result. If the operand is an unsupported
data type (denormalized, unnormalized, or packed decimal real), the unimplemented
floating-point exception takes precedence, and the floating-point instruction emulation
routine must detect the unsupported data type.
The processor begins exception processing for the unimplemented floating-point
instruction by making an internal copy of the current SR. The processor then enters the
supervisor mode and clears the trace bits (T1, T0). The processor creates a format $2
stack frame and saves the vector offset, PC, internal copy of the SR, and calculated
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