MC68LC040RC25A Datasheet, PDF (71/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
Table 3-1. Updating U-Bit and M-Bit for Page Descriptors
Previous Status
Access
U-Bit M-Bit WP Bit ^Type
Page Descriptor
Update Operation
0
0
Locked RMW Access to Set U
0
1
Locked RMW Access to Set U
1
0
X
Read None
1
1
None
0
0
Write to Set U and M
0
1
Locked RMW Access to Set U
1
0
0
Write to Set M
1
1
Write None
0
0
Locked RMW Access to Set U
0
1
Locked RMW Access to Set U
1
0
1
None
1
1
None
NOTE: WP indicates the accumulated write-protect status.
New Status
U-Bit M-Bit
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
An alternate address space access is a special case that is immediately used as a
physical address without translation. Because the M68040 implements a merged
instruction and data space, the integer unit translates MOVES accesses to instruction
address spaces (SFC/DFC = $6 or $2) into data references (SFC/DFC = $5 or $1). The
data memory unit handles these translated accesses as normal data accesses. If the
access fails due to an ATC fault or a physical bus error, the resulting access error stack
frame contains the converted function code in the TM field for the faulted access.
Invalidation of the instruction cache line containing the referenced location to maintain
cache coherency must precede MOVES accesses that write the instruction address
space. The SFC and DFC values and results are listed in Table 3-2.
Table 3-2. SFC and DFC Values
SFC/DFC Value
000
001
010
011
100
101
110
111
Results
TT
TM
10
000
00
001
00
001
10
011
10
100
00
101
00
101
10
111
3-22
M68040 USER'S MANUAL
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