MC68LC040RC25A Datasheet, PDF (53/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
0 of an address loaded into the URP or the SRP must be zero. Transfers of data to and
from these 32-bit registers are long-word transfers.
31
98
0
USER ROOT POINTER
000000000
SUPERVISOR ROOT POINTER
000000000
Figure 3-3. URP and SRP Register Formats
3.1.2 Translation Control Register
The 16-bit TCR contains two control bits to enable paged address translation and to select
page size. The operating system must flush the ATCs before enabling address translation
since the TCR accesses and reset do not flush the ATCs. All unimplemented bits of this
register are read as zeros and must always be written as zeros. The M68040 always uses
word transfers to access this 16-bit register. The fields of the TCRs are defined following
Figure 3-4, which illustrates the TCR.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EP0 0 0 0 0 0 0 0 0 0 0 0 0 0
NOTE: Bits 13–0 are undefined (reserved).
Figure 3-4. Translation Control Register Format
E—Enable
This bit enables and disables paged address translation.
0 = Disable
1 = Enable
A reset operation clears this bit. When translation is disabled, logical addresses are
used as physical addresses. The MMU instruction, PFLUSH, can be executed
successfully despite the state of the E-bit. PTEST results are undefined if the MMU is
disabled and no table search occurs. If translation is disabled and an access does not
match a transparent translation register (TTR), the access has the following default
attributes on the TTR: the caching mode is cachable/write-through, write protection is
disabled, and the user attribute signals (UPA1 and UPA0) are zero.
P—Page Size
This bit selects the memory page size.
0 = 4 Kbytes
1 = 8 Kbytes
A reset operation does not affect this bit. The bit must be initialized after a reset.
3-4
M68040 USER'S MANUAL
MOTOROLA
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