MC68LC040RC25A Datasheet, PDF(115/442 Page) Freescale Semiconductor, Inc – M68040 Users Manual

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MC68LC040RC25A Datasheet, PDF (115/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

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Freescale Semiconductor, Inc.

Table 5-6. Processor Status Encoding

Hex PST3 PST2 PST1 PST0

Internal Status

0

0

0

0

0 User, Start/Continue Current Instruction

1

0

0

0

1 User, End Current Instruction

2

0

0

1

0 User, Branch Not Taken/End Current Instruction

3

0

0

1

1 User, Branch Taken/End Current Instruction

4

0

1

0

0 User, Table Search

5

0

1

0

1 Halted State (Double Bus Fault)

6

0

1

1

0 Low-Power Stop Mode (Supervisor Instruction)*

7

0

1

1

1 Reserved

8

1

0

0

0 Supervisor, Start/Continue Current Instruction

9

1

0

0

1 Supervisor, End Current Instruction

A

1

0

1

0 Supervisor, Branch Not Taken/End Current Instruction

B

1

0

1

1 Supervisor, Branch Taken/End Current Instruction

C

1

1

0

0 Supervisor, Table Search

D

1

1

0

1 Stopped State (Supervisor Instruction)

E

1

1

1

0 RTE Executing

F

1

1

1

1 Exception Stacking

NOTE: *MC68040V and MC68EC040V only.

When a âbranch taken/end current instructionâ is indicated, it means that a change of

instruction flow is pending. Along with the following instructions, an exception stacking

(encoding F) sequence is ended with the âsupervisor, branch taken/end current instructionâ

encoding as though it were a virtual JMP instruction. This includes all the possible

exceptions listed in the processorâs vector table. Instructions that cause a âbranch

taken/end current instructionâ encoding when they are executed are as follows:

ANDI to SR

Bcc (Taken)

BRA

BSR

CAS

CAS2

CINV

CPUSH

DBcc (Taken)

FBcc (Taken)

FDBcc (Always)

FMOVEM Rc,MRn

FMOVEM FPm,MRn

FSAVE

JMP

JSR

MOVE to SR

MOVE USP

MOVEC

MOVES

NOP

ORI to SR

PFLUSH

PTEST

RTD

RTE

RTR

RTS

STOP

TAS

The Bcc (not taken) and DBcc (not taken) are the only instructions that cause a âbranch

not taken/end current instructionâ encoding. Note that the FBcc (not taken) is not included

in this category. The FBcc (not taken) instruction ends with an âend current instructionâ

encoding. All other instructions and conditions end with the âend current instructionâ

encoding. For instance, if the processor is running back-to-back single clock instructions,

the encoding âend current instructionâ remains asserted for as many clock cycles as

instructions.

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M68040 USERâS MANUAL

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