MC68LC040RC25A Datasheet, PDF (227/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
EXTERNAL
IPL2–IPL0
100 ($3)
IF
001 ($6)
INTERRUPT PRIORITY
MASK (I2–I0)
101 ($5)
ACTION
THEN
110 ($6)
AND LEVEL 6 INTERRUPT
(INITIAL CONDITIONS)
(LEVEL COMPARISON)
IF
100 ($3)
AND STILL
110 ($6)
THEN NO ACTION
IF
001 ($6)
AND STILL
110 ($6)
THEN NO ACTION
IF STILL 001 ($6)
AND RTE SO THAT
101 ($5)
THEN LEVEL 6 INTERRUPT ^{(LEVEL COMPARISON)}
100 ($3)
101 ($5)
(INITIAL CONDITIONS)
IF
000 ($7)
THEN
111 ($7)
AND LEVEL 7 INTERRUPT
(TRANSITION)
IF
100 ($3)
AND STILL
111 ($7)
THEN NO ACTION
IF
000 ($7)
AND STILL
111 ($7)
THEN NO ACTION
(TRANSITION)
IF STILL 000 ($7)
AND RTE SO THAT
101 ($5)
THEN LEVEL 7 INTERRUPT (LEVEL COMPARISON)
Figure 8-3. Interrupt Recognition Examples
Note that a mask value of 6 and a mask value of 7 both inhibit request levels of 1–6 from
being recognized. In addition, neither masks a transition to an interrupt request level of 7.
The only difference between mask values of 6 and 7 occurs when the interrupt request
level is 7 and the mask value is 7. If the mask value is lowered to 6, a second level 7
interrupt is recognized.
External circuitry can chain or otherwise merge signals from devices at each level,
allowing an unlimited number of devices to interrupt the processor. When several devices
are connected to the same interrupt level, each device should hold its interrupt priority
level constant until its corresponding interrupt acknowledge bus cycle ensures that all
requests are processed. Refer to Section 7 Bus Operation for details on the interrupt
acknowledge cycle.
8-14
M68040 USER’S MANUAL
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