MC68LC040RC25A Datasheet, PDF (291/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
Table 9-16. State Frame Field Information (Concluded)
FSAVE State
Frame Field
Contents
INEX (FMOVE to Register, FABS, and FNEG)
CMDREG1B
Exception Instruction Command Word
FPTEMP
Unrounded, Extended-Precision Intermediate Result
STAG
Source Operand Tag = Normalized
E1
Always 1
T
Always 0
INEX (FADD, FSUB, FMUL, FDIV, and FSQRT)
CMDREG3B
Encoded Exception Instruction Command Word
WBTEMP
WBTS, WBTE, and WBTM = intermediate result sign, biased 15-bit
exponent, and 64-bit mantissa prior to rounding.
WBTE15
Either 1 or 0, generally useless for INEX exceptions.
WBTM1, WBTM0, Guard, round, and sticky of intermediate result’s 67-bit mantissa.
SBIT
E3
Always 1
T
Either 1 or 0
INEX (FMOVE to Memory)
CMDREG1B
FMOVE Instruction Command Word
FPTEMP
Intermediate result with mantissa prior to rounding.
STAG
Source Operand Tag = Normalized
E1
Always 1
T
Always 1
NOTE: If the M68040FPSP unimplemented exception handler is used, the above state frame
information applies. The CMDREG1B or CMDREG3B fields of the state frame are modified as
appropriate to encode the unimplemented instruction opcode. It is the user exception handler’s
responsibility to use the E3 and E1 field encodings to recognize which state frame information
applies. When E3 = 1 and E1 = 1, E3 takes priority and the state frame information for E3 = 1
must be used.
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M68040 USER’S MANUAL
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