MC68LC040RC25A Datasheet, PDF (166/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
BCLK
A31–A4
C1
C2
C3
C4
C5
A3
A2–A0
UPA1, UPA0
SIZ1, SIZ0
TT1, TT0
TM2–TM0
R/W
CIOUT
TS
TIP
TA
D31–D0
A3, A2 =
01
10
11
00
NOTE: The selected device increments the value of A3 and A2.
Figure 7-17. Line Write Transfer Timing
Clock 1 (C1)
The line write cycle starts in C1. During the first half of C1, the processor places valid
values on the address bus and transfer attributes. For user and supervisor mode
accesses that are translated by the corresponding memory unit, UPAx signals are
driven with the values from the matching U1 and U0 bits. The TTx and TMx signals
identify the specific access type. The R/W signal is driven low for a write cycle, and
SIZ1 and SIZ0 indicate line size. CIOUT is asserted for a MOVE16 operand read if the
access is identified as noncachable. Refer to Section 3 Memory Management Unit
(Except MC68EC040 and MC68EC040V) for information on the M68040 and
7-24
M68040 USER’S MANUAL
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