MC68LC040RC25A Datasheet, PDF (280/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

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is set, the floating-point frame is discarded. The RTE instruction must be executed to
return to normal instruction flow.
9.7.6 Divide by Zero
This exception happens when a zero divisor occurs for a divide instruction or when a
transcendental function is asymptotic with infinity as the asymptote. Table 9-14 lists the
instructions that can cause the divide by zero exception. Note that only the FDIV and
FSGLDIV instructions are native to the MC68040. The other conditions occur only if the
M68040FPSP is used. When a divide by zero is detected, the DZ bit is set in the FPSR
EXC byte. The divide by zero exception only has maskable exceptional conditions;
therefore, no M68040FPSP intervention is needed. An exception is taken only if the DZ bit
is set in FPSR EXC byte and the corresponding bit in the FPCR ENABLE byte is set.
a. If the user divide by zero exception handler is enabled, an infinity with the sign set to
the exclusive OR of the signs of the input operands is stored in the destination
floating-point data register. No exception is taken.
b. If the user divide by zero exception handler is disabled, the destination floating-point
data register is not modified, and the exception is reported as a pre-instruction
exception when the next floating-point instruction is attempted. The divide by zero
entry in the processor’s vector table points to the user divide by zero exception
handler.
Table 9-14. Possible Divide by Zero Exceptions
Instruction
FDIV
FLOG10
FLOG2
FLOGN
FTAN
FSGLDIV
Operand Value
Source operand = 0 and floating-point data register is not a NAN
Source operand = 0
Source operand = 0
Source operand = 0
Source operand is an odd multiple of ±π ÷ 2
Source operand = 0 and floating-point data register is not a NAN
An FSAVE must be the first instruction of the user divide by zero exception handler. The
user divide by zero exception handler must generate a result to store in the destination. To
assist the exception handler in this function, the processor supplies the information listed
in Table 9-16, which lists the floating-point state frame fields for divide by zero exceptions
that are defined for supervisor exception handler use. To exit the user divide by zero
exception handler, the saved floating-point frame is discarded, and an RTE returns the
processor to normal processing.
9.7.7 Inexact Result
The processor provides two inexact bits in the FPSR EXC byte to help distinguish
between inexact results generated by emulated decimal input (INEX1 exceptions) and
other inexact results (INEX2 exceptions). These two bits are useful in instructions where
both types of inexact results can occur (e.g., FDIV.P #7E-1,FP3). In this case, the packed
decimal to extended-precision conversion of the immediate source operand causes an
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