MC68LC040RC25A Datasheet, PDF (386/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
MC68EC040 REV2.3 (01/31/2000)
direct addressing modes, this field is $0. The saved PC value is the logical address of
the instruction that follows the unimplemented floating-point instruction. This value will
be restored during RTE execution. The vector offset format number ($4) is used for
this eight-word stack frame. Note that an MC68040 cannot correctly handle a stack for-
mat $4. The PC of the faulted instruction contains a long-word PC of the floating-point
instruction that caused the trap to occur. The information is provided so that the in-
struction is available for software emulation of floating-point instructions. The proces-
sor generates exception vector number 11 for the unimplemented F-line instruction
exception vector, fetches the address of the F-line exception handler from the excep-
tion vector table, and begins execution of the handler after prefetching instructions to
fill the pipeline. Refer to Section 8 Exception Processing for details about exception
processing.
B.5.2 MC68EC040 Stack Frames
When the processor executes an RTE instruction, it examines the stack frame on top of the
active supervisor stack to determine if it is a valid frame and what type of context restoration
it requires. The set of stack frames included for exception processing are four- and six-word
stack frames, a four-word throwaway stack frame, an access error stack frame, and a new
eight-word unimplemented floating-point stack frame. The stack frame that the MC68040
can generate and the MC68EC040 can process is the floating-point post-instruction stack
frame. Refer to Section 8 Exception Processing for details about exception stack frames.
Eight-Word Stack Frame (Format $4)
Stack Frames
15
SP
+$02
+$06
+$08
STATUS REGISTER
PROGRAM COUNTER
0100
VECTOR OFFSET
EFFECTIVE ADDRESS
+$0C
PC OF FAULTED
INSTRUCTION
Exception Types
Stacked PC Points To
• The MC68040 cannot
• Effective address field is
generate or read this stack.
0
the address of the faulted
instruction operand.
When the MC68EC040 writes or reads a stack frame, it uses long-word operand transfers
wherever possible. Using a long-word-aligned stack pointer greatly enhances exception pro-
cessing performance. The processor does not necessarily read or write the stack frame data
in sequential order. The system software should not depend on a particular exception gen-
erating a particular stack frame. For compatibility with future devices, the software should be
able to handle any type of stack frame for any type of exception. The MC68EC040 does not
generate the floating-point post-instruction stack frame. The MC68040 cannot accept the
eight-word unimplemented stack frame. The MC68EC040 can handle all MC68040 stack
frame formats.
B.6 SOFTWARE CONSIDERATIONS
The following MC68EC040 instructions are different from the MC68040: PTEST, PFLUSH,
CPUSH, CINV, MOVEC, and all floating-point instructions.
B-10
M68040 USER’S MANUAL
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