MC68LC040RC25A Datasheet, PDF (86/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
memory is always updated through an external bus access after updating the cache,
keeping memory and cached data consistent.
INSTRUCTION DATA BUS
CONVERT
EXECUTE
WRITE-
BACK
FLOATING-
POINT UNIT
INSTRUCTION
FETCH
DECODE
EA
CALCULATE
EA
FETCH
EXECUTE
WRITEBACK
INTEGER
UNIT
INSTRUCTION
ATC
INSTRUCTION
CACHE
INSTRUCTION
MMU/CACHE/SNOOP
CONTROLLER
INSTRUCTION MEMORY UNIT
DATA MEMORY UNIT
DATA
MMU/CACHE/SNOOP
CONTROLLER
INSTRUCTION
ADDRESS
B
U
S
C
O
N
T
R
O
L
DATA
L
ADDRESS
E
R
DATA
ATC
DATA
CACHE
ADDRESS
BUS
DATA
BUS
BUS
CONTROL
SIGNALS
OPERAND DATA BUS
Figure 4-1. Overview of Internal Caches
4.1 CACHE OPERATION
Both four-way set-associative caches have 64 sets of four 16-byte lines. There are two
formats that define each cache line, an instruction cache line format and a data cache line
format. Each format contains an address tag consisting of the upper 22 bits of the physical
address, status information, and four long words (128 bits) of data. The status information
for the instruction cache line address tag consists of a single valid bit for the entire line.
The status information for the data cache line address tag contains a valid bit and four
additional bits to indicate dirty status for each long word in the line. Note that only the data
cache supports dirty cache lines. Figure 4-2 illustrates the instruction cache line format (a)
and the data cache line format (b).
4-2
M68040 USER'S MANUAL
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