MC68LC040RC25A Datasheet, PDF (194/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
C1
C2
C3
C4
C5
C6
C7
C8
C9
BCLK
A31–A0
TRANSFER
ATTRIBUTES
TS
TIP
TA
D31–D0
BR
BG
BB
AM_BR*
AM_BG*
ALTERNATE
MASTER
*AM indicates the alternate bus master.
Undefined
BUS
IMPLICITLY
OWNED
BUS OWNED
AND ACTIVE
PROCESSOR
BUS OWNED
AND IDLE
Figure 7-34. Implicit Bus Ownership Arbitration Timing
7.8.2 Bus Arbitration Examples
The following paragraphs illustrate the behavior of the M68040 bus arbitration scheme
and provide examples of how an external bus arbiter can be designed to keep the integrity
of locked bus operations. The examples include the previously mentioned indeterminate
and disregard request conditions.
7.8.2.1 DUAL M68040 FAIRNESS ARBITRATION. The following state diagram illustrates
a fairness algorithm using two MC68040s and assigning the least priority to the processor
that owns the bus. If both processors keep their respective BR signals asserted, bus
ownership alternates between the two processors so that each processor can run at least
one bus cycle during its tenure. Each processor is allowed to own the bus without
relinquishing it to maintain the integrity of locked transfers. This example also illustrates
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M68040 USER’S MANUAL
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