MC68LC040RC25A Datasheet, PDF (113/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
MC68040 Floating-Point Emulation (MC68040FPSP) for descriptions of emulator use of
this signal.
5.7.2 Reset In (RSTI)
This input signal causes the M68040 to enter reset exception processing. The RSTI signal
is an asynchronous input that is internally synchronized to the next rising edge of the
BCLK signal. All three-state signals are set to the high-impedance state, and all outputs,
except MI, are negated when RSTI is recognized. The assertion of RSTI does not affect
the test pins. Refer to Section 7 Bus Operation for a description of reset operation and to
Section 8 Exception Processing for information about the reset exception.
5.7.3 Reset Out (RSTO)
The M68040 asserts this output during execution of the RESET instruction to initialize
external devices. Refer to Section 7 Bus Operation for a description of reset out bus
operation.
5.8 INTERRUPT CONTROL SIGNALS
The following signals control the interrupt functions.
5.8.1 Interrupt Priority Level (IPL2–IPL0)
These input signals provide an indication of an interrupt condition and the encoding of the
interrupt level from a peripheral or external prioritizing circuitry. IPL2is the most significant
bit of the level number. For example, since the IPL¯signals are active low, IPL2–IPL0 = $5
corresponds to an interrupt request at interrupt priority level 2.
During a processor reset, the levels on the IPL¯lines are latched and used to select the
output driver characteristics for three signal groups listed in Table 5-5. Refer to Section 8
Exception Processing for information on interrupts and to Section 11 MC68040
Electrical and Thermal Characteristics for information on driver characteristics. Refer to
Appendix A MC68LC040 and Appendix B MC68EC040 for how these signals are
different on power-up.
Table 5-5. Output Driver Control Groups
Signal
Output Buffers Controlled
IPL2 Data-Bus: D31–D0
IPL1
Address Bus and Transfer Attributes:
A31–A0, CIOUT, LOCK, LOCKE , R/ W, SIZ1–SIZ0,
TLN1–TLN0, TM2–TM0, TT1–TT0, UPA1–UPA0
IPL0
Miscellaneous Control Signals:
BB, BR , IPEND, MI, PST3–PST0, RSTO , TA, TDO, TIP, TS
NOTE: High input level = small buffers enabled; low input level = large buffers enabled.
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