MC68LC040RC25A Datasheet, PDF (398/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
Table C-1. Additional MC68040V and MC68EC040V Signals
Signal Name
Low Frequency
Operation
Loss of Clock
System Clock Disable
Mnemonic
Function
LFO
Used to enter the low frequency mode of operation.
LOC
SCD
Indicates loss of BCLK input, a reset is required
Indicates normal operation is suspended and low-power stop mode is active,
system logic may remove or change the frequency of the BCLK input.
C.1.1 Low Frequency Operation (LFO)
When asserted, this input signal allows the frequency of BCLK to be changed
instantaneously (0 to 16 MHz) providing minimum pulse width constraints are met (see
C.7 MC68040V and MC68EC040V Electrical Characteristics. LFO is only recognized
during low-power stop mode and reset.
C.1.2 Loss of Clock (LOC)
Whenever the internal clock circuitry detects either a phase lock error or a loss of BCLK,
this output signal is driven high (only during normal mode of clocking operation). LOC is
also three-stated during reset, low-power stop, or low frequency operation. There should
be a pull-down resistor on the system board to ground.
C.1.3 System Clock Disable (SCD)
When asserted this output signal indicates, when asserted, that the BCLK input can be
disabled or changed in frequency. SCD is asserted upon termination of the LPSTOP
broadcast cycle. BCLK must be stable when SCD is negated, in accordance with the
specifications in C.7 MC68040V and MC68EC040V Electrical Characteristics.
C-2
M68040 USER’S MANUAL
MOTOROLA
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