MC68LC040RC25A Datasheet, PDF (213/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

BCLK
DLE
D0–D31 IN
(READ)
TA
Freescale Semiconductor, Inc.
CASE 1
DLE MODE DATA BUS TIMING
CASE 2
35
36
37
31
34
33
32
36
NORMAL DATA BUS TIMING
BCLK
15
D0–D31 IN
(READ)
16
TA
Figure 7-48. DLE versus Normal Data Read Timing
Case 1
If DLE is negated and meets setup time specification #35 to the rising edge of BCLK
when the bus read is terminated, latch A is transparent, and the read data must meet
setup and hold time specifications #36 and #37 to the rising edge of BCLK. Read timing
is similar to normal timing for this case.
Case 2
If DLE is asserted, the data bus levels are latched and held internally. D31–D0 must
meet setup and hold time specifications #32 and #33 to the falling edge of DLE, and can
transition to a new level once DLE is asserted. D31–D0 must still meet setup time
specification #36 to BCLK, but not hold time specification #37, since the data is
internally held valid as long as DLE remains asserted low.
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M68040 USER’S MANUAL
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