MC68LC040RC25A Datasheet, PDF (244/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
Table 8-6. Access Error Stack Frame Combinations
WB1S
Main Case SSW_RW SSW_PUSH _{1V 1M16}
All Read
1a
Access Errors 1a
No
0X
No
0X
WB2S
2V 2M16
0X
0X
WB3S
3V
0
1
Easy Cleanup
Data Written
None
WB3D
Hard Cleanup
Action
(Note b)
All other read cases are not possible.
Cache Push
0
Physical Bus
0
Error ^c
0
0
0
Yes
0X 0X
0 PD3–0
Yes
0X 0X
1 PD3–0, WB3D
Yes
0X 1 0
0 PD3–0, WB2D
Yes
0X 1 0
1 PD3–0, WB2D, WB3D
Yes
0X 1 1
0 PD3–0, ~WB2Dd
(Note b)
Normal Write
0
Physical bus
0
Error
0
0
0
No
1 0 0X
0 WB1D
No
1 0 0X
1 WB1D, WB3D
No
1010
0 WB1D, WB2D
No
1010
1 WB1D, WB2D, WB3D
No
1011
0 WB1D, ~WB2Dd
(Note b)
MOVE16
0
Write Physical
0
Bus Error
0
0
0
No
1 1 0X
1 PD3–0, WB3D
No
1 1 0X
0 PD3–0
No
1110
0 PD3–0, WB2D
No
1110
1 PD3–0, WB2D, WB3D
No
1111
0 PD3–0, ~WB2Dd
(Note b)
Write Page
0
Fault
0
0
No
0X 1 0
0 WB2D
No
0X 1 0
1 WB2D, WB3D
No
0X 1 1
0 ~WB2Dd
Write PD3–0
and skipe.
Impossible
0
Yes
1XXX
X (Note f)
—
Write Cases
0
Don't Care X X X 1
1 (Note g)
NOTES:
a. The data memory unit stage is tied up until the bus controller passes the read back through the data memory
unit and to the execution stage in the integer unit. Therefore, no pending write is possible in WB1 or WB2.
WB3 could hold a pending write that was deferred due to operand read or was generated after the read.
b. If any kind of access error is reported and if a MOVE16 write is pending in the WB2 stage, then that MOVE16
read must hit in the cache so the MOVE16 can be safely restarted since it has not caused bus cycles that could
retouch peripherals.
c. A cache push physical bus error is normally considered a fatal error. For these cases, the FA field is a physical
address, not a logical address as in the other cases.
d. Indicates that the data should not be written even though the V-bit for it is set (WB2 corresponds to a MOVE16
write).
e. The exception handler must alter the stacked PC to point past the MOVE16 and predecrement and
postincrement address registers.
f. 1V must be 0 for push exceptions.
g. The execution stage does not post a write until the MOVE16 is in the integer unit.
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