MC68LC040RC25A Datasheet, PDF (106/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
ADDRESS
BUS
DATA BUS
TRANSFER
ATTRIBUTES
MASTER
TRANSFER
CONTROL
SLAVE
TRANSFER
CONTROL
A31–A0
D31–D0
TT0
TT1
TM0
TM1
TM2
TLN0
TLN1
UPA0
UPA1
R/W
SIZ0
SIZ1
LOCK
LOCKE
CIOUT
TS
TIP
TA
TEA
TCI
TBI
DLE1
MC68040
SC0
SC1
MI
BR
BG
BB
CDIS
MDIS2
RSTI
RSTO
IPL03
IPL13
IPL23
IPEND
AVEC
PST0
PST1
PST2
PST3
BCLK
PCLK4
TCK
TMS
TDI
TDO
TRST4
V_CC
GND
BUS SNOOP CONTROL
AND RESPONSE
BUS ARBITRATION
PROCESSOR
CONTROL
INTERRUPT
CONTROL
STATUS AND
CLOCKS
TEST
POWER SUPPLY
NOTES:
1. This signal is only available on the MC68040.
2. This signal is not available on the MC68EC040 and MC68EC040V.
3. These signals are different on power-up for the MC68LC040 and MC68EC040.
4. These signals are not available on the MC68040V and MC68EC040V.
Figure 5-1. Functional Signal Groups
5.1 ADDRESS BUS (A31–A0)
These three-state bidirectional signals provide the address of the first item of a bus
transfer (except for acknowledge transfers) when the M68040 is the bus master. When an
alternate bus master is controlling the bus, the processor examines (snoops) these signals
to determine whether the processor should intervene in the access to maintain cache
coherency.
The level on CDIS can select a multiplexed bus mode during processor reset, which
allows the address bus and data bus to be physically tied together for multiplexed bus
5-4
M68040 USER’S MANUAL
MOTOROLA
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