MC68LC040RC25A Datasheet, PDF (223/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

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executing the instruction. As illustrated in Figure 8-1, the processor copies the SR, enters
the supervisor mode, and clears the trace bits. The processor generates vector number 8,
saves the privilege violation vector offset, the current PC value, and the internal copy of
the SR on the supervisor stack. The saved value of the PC is the logical address of the
first word of the instruction that caused the privilege violation. Instruction execution
resumes after the required prefetches from the address in the privilege violation exception
vector.
8.2.6 Trace Exception
To aid in program development, the M68000 family includes an instruction-by-instruction
tracing capability. The M68040 can be programmed to trace all instructions or only
instructions that change program flow. In the trace mode, an instruction generates a trace
exception after the instruction completes execution, allowing a debugging program to
monitor execution of a program.
In general terms, a trace exception is an extension to the function of any traced
instruction. The execution of a traced instruction is not complete until trace exception
processing is complete. If an instruction does not complete due to an access fault or
address error exception, trace exception processing is deferred until after execution of the
suspended instruction is resumed. If an interrupt is pending at the completion of an
instruction, trace exception processing occurs before interrupt exception processing starts.
If an instruction forces an exception as part of its normal execution, the forced exception
processing occurs before the trace exception is processed.
The T1 and T0 bits in the supervisor portion of the SR control tracing. The state of these
bits when an instruction begins execution determines whether the instruction generates a
trace exception after the instruction completes. T1 and T0 bit = $1 causes an instruction
that forces a change of flow to take a trace exception. The following instructions cause a
trace exception to be taken when trace on change of flow is enabled.
ANDI to SR
Bcc (Taken)
BRA
BSR
CAS
CAS2
FBcc (Taken)
CINV
FDBcc (Always)
CPUSH
FMOVEM
DBcc (Taken) FRESTORE
EORI to SR FSAVE
JMP
JSR
MOVE to SR
MOVE USP
MOVEC
MOVES
NOP
ORI to SR
PFLUSH
PTEST
RTD
RTE
RTR
RTS
STOP
Instructions that increment the PC normally do not take the trace exception. This mode
also includes SR manipulations because the processor must prefetch instruction words
again to fill the pipeline any time an instruction that modifies the SR is executed. Table 8-2
lists the different trace modes.
8-10
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