MC68LC040RC25A Datasheet, PDF (183/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
7.6.2 Retry Operation
When an external device asserts both the TA and TEA signals during a bus cycle, the
processor enters the retry sequence. The processor terminates the bus cycle and
immediately retries the cycle using the same access information (address and transfer
attributes). However, if the bus cycle was a cache push operation, the bus is arbitrated
away from the M68040 before the retry operation, and a snoop during the arbitration
invalidates the cache push, then the processor does not use the same access information.
Figure 7-28 illustrates a functional timing diagram for a retry of a read bus transfer.
C1
C2
CW
C1
C2
BCLK
A31–A0
UPA1, UPA0
SIZ1, SIZ0
LONG WORD
TT1, TT0
TM2–TM0
R/W
CIOUT
TS
TIP
TA
TEA
D31–D0
READ CYCLE
RETRY SIGNALED
RETRY
CYCLE
Figure 7-28. Retry Read Transfer Timing
The processor retries any read or write cycles of a read-modify-write transfer separately;
LOCK remains asserted during the entire retry sequence. If the last bus cycle of a locked
access is retried, LOCKE remains asserted through the retry of the write cycle.
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