MC68LC040RC25A Datasheet, PDF (23/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
• The DLE pin name has been changed to JS0 on both the MC68040V and
MC68LC040. In addition, the MC68040V contains three new pins, system clock
disable (SCD ), low frequency operation (LFO), and loss of clock (LOC ).
• The MC68040V and MC68LC040 do not implement the data latch enable (DLE),
multiplexed, or output buffer impedance selection modes of operation. They
implement only the small output buffer mode of operation. All timing and drive
capabilities on both devices are equivalent to those of the MC68040 in small output
buffer impedance mode. The MC68040V has an additional mode of operation, the
low-power stop mode of operation.
• The MC68040V and MC68LC040 do not contain an FPU, causing unimplemented
floating-point exceptions to occur using a new stack frame format.
• The MC68040V is a 3.3 volt static microprocessor that operates down to 0 MHz.
For specific details on the MC68LC040, refer to Appendix A MC68LC040. For specific
details on the MC68040V, refer to both Appendix A MC68LC040 and Appendix C
MC68040V and MC68EC040V. Disregard all information concerning the FPU when
reading the following subsections.
1.1.2 MC68EC040 and MC68EC040V
The MC68EC040 and MC68EC040V are derivatives of the MC68040. They implement the
same IU as the MC68040, but have no FPU or MMU, which embedded control
applications generally do not require. The MC68EC040 is pin compatible with the
MC68040. The following differences exist between the MC68EC040, MC68EC040V, and
the MC68040:
• The DLE and MDIS pin names have been changed to JS0 and JS1, respectively.
• PTEST and PFLUSH instructions cause an undetermined number of bus cycles; the
user should not execute these instructions.
• The access control unit (ACU) replaces the MMU. The MC68EC040 and
MC68EC040V ACU has two data and two instruction registers that are called data
and instruction transparent translation registers in the MC68040.
• The MC68EC040 and MC68EC040V do not implement the DLE, multiplexed, or
output buffer impedance selection modes of operation. They only implement the small
output buffer mode of operation. All MC68EC040 and MC68EC040V timing and drive
capabilities are equivalent to the MC68040 in small output buffer mode.
• The MC68EC040 and MC68EC040V do not contain an FPU, causing unimplemented
floating-point exceptions to occur using a new stack frame format.
• The MC68040V is a 3.3 volt static microprocessor that operates down to 0 MHz.
Refer to Appendix B MC68EC040 for specific details on the MC68EC040. Refer to
Appendix B MC68EC040 and Appendix C MC68040V and MC68EC040V for specific
details on the MC68EC040V. Disregard information concerning the FPU and MMU
when reading the following subsections.
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M68040 USER’S MANUAL
MOTOROLA
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