MC68LC040RC25A Datasheet, PDF (290/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
Table 9-16. State Frame Field Information (Continued)
FSAVE State
Frame Field
Contents
OVFL (FMOVE to Memory)
CMDREG1B
FMOVE instruction command word
FPTEMP
Intermediate result with mantissa rounded to correct precision.
STAG
Source Operand Tag = Normalized
E1
Always 1
T
Always 1
UNFL (FMOVE to Register, FABS, and FNEG)
CMDREG1B
Exception Instruction Command Word
FPTEMP
Unrounded, Extended-Precision Intermediate Result
STAG
Source Operand Tag = Normalized
E1
Always 1
T
Always 0
UNFL (FADD, FSUB, FMUL, FDIV, and FSQRT)
CMDREG3B
Encoded Exception Instruction Command Word
WBTEMP
WBTS, WBTE, and WBTM = intermediate result sign, biased 15-bit
exponent, and 64-bit mantissa prior to rounding.
WBTE15
Bit 15 of the intermediate result's 16-bit exponent = 1 for underflow.
WBTM1, WBTM0, Guard, round, and sticky of intermediate result’s 67-bit mantissa.
SBIT
E3
Always 1
T
Either 1 or 0
UNFL (FMOVE to Memory)
CMDREG1B
FMOVE Instruction Command Word
FPTEMP
Intermediate result with mantissa prior to rounding.
STAG
Source Operand Tag = Normalized
E1
Always 1
T
Always 1
DZ
CMDREG1B
M68040FPSP divide by zero can generate.
ETEMP
Source operand is converted to extended precision.
STAG
Source Operand Tag
FPTEMP
Destination operand is converted to extended precision.
E1
Always 1
T
Always 0
9-46
M68040 USER’S MANUAL
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