MC68LC040RC25A Datasheet, PDF (379/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
MC68EC040 REV2.3 (01/31/2000)
31
0
D0
D1
D2
DATA
REGISTERS
D3
D4
D5
D6
D7
ADDRESS
REGISTERS
A0
A1
A2
A3
A4
A5
A6
A7/USP
PC
CCR
USER STACK POINTER
PROGRAM COUNTER
CONDITIONAL CODE REGISTER
USER PROGRAMMING MODEL
31
0
A7’/ISP
A7”/MSP
(CCR) ^SR
VBR
SFC
DFC
CACR
URP
SRP
TC
DTT0
DTT1
ITT0
ITT1
MMUSR
INTERRUPT STACK POINTER
MASTER STACK POINTER
STATUS REGISTER
VECTOR BASE REGISTER
SOURCE FUNCTION CODE
DESTINATION FUNCTION CODE
CACHE CONTROL REGISTER
USER ROOT POINTER REGISTER
SUPERVISOR ROOT POINTER REGISTER
TRANSLATION CONTROL REGISTER
DATA TRANSPARENT TRANSLATION REGISTER 0
DATA TRANSPARENT TRANSLATION REGISTER 1
INSTRUCTION TRANSPARENT TRANSLATION REGISTER 0
INSTRUCTION TRANSPARENT TRANSLATION REGISTER 1
MMU STATUS REGISTER
SUPERVISOR PROGRAMMING MODEL
Figure B-2. MC68EC040 Programming Model
• PTEST and PFLUSH instructions cause an indeterminate result (i.e., an undetermined
number of bus cycles); the user should not execute them on the MC68EC040.
• The MC68EC040 does not contain an FPU which causes unimplemented floating-point
exceptions to occur using a new stack frame format.
• The DLE and MDIS pin names have been changed to JS0 and JS1, respectively.
• The MC68EC040 does not implement the DLE mode, multiplexed, or output buffer im-
pedance selection modes of operation. The MC68EC040 implements only the small
output buffer mode of operation. All timing and drive capabilities of the MC68EC040 are
equivalent to those of the MC68040 in the small buffer mode of operation.
B.2 JTAG SCAN (JS1–JS0)
The MC68040 MDIS and DLE pin names have been changed to JS1 and JS0 respectively.
During normal operation, the JS1 and JS0 pin cannot float, they must be tied to GND or Vcc
directly or through a resistor. During board testing, these pins retain the functionality of the
JTAG scan of the MC68040 for compatibility purposes. Refer to Section 6 IEEE 1149.1A
MOTOROLA
M68040 USER’S MANUAL
B-3
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